1. Field of the Invention
This invention relates to integrated circuit design; in particular this invention relates to the design of universal asynchronous receiver/transmitter (UART) integrated circuits.
2. Discussion of the Related Art
UARTs have been used in the past in input and output ports of a computer system to convert byte-parallel data received from a central process unit (CPU) of the computer system to serial data for transmission over a serial link. One example of a prior art UART is the NS16550, available from National Semiconductor Corporation. The NS16550 is described in detail in U.S. Pat. No. 5,140,679 to Michael, entitled "Universal Synchronous Receiver/Transmitter", issued on Aug. 18, 1992, and filed on Sep. 14, 1988. The disclosure of U.S. Pat. No. 5,140,679 is hereby incorporated by reference in its entirety as background information.
In the past, "software flow control" is established for ASCII transfer modes using the "XON" and "XOFF" characters, which are respectively assigned ASCII codes '11H and '13H, to indicate "start" and "stop" flow control. The term "software flow control" refers to the flow control mechanism in which flow control characters are embedded in the data stream. Under an ASCII transfer mode, the receiver sends an XOFF character to the transmitter when the number of characters in the receiver's first-in-first-out memory (FIFO), which contains data received from the transmitter, exceeds a pre-determined trigger level. Upon receiving the XOFF character, the transmitter suspends transmission after transmitting the current character and waits for an XON character from the receiver. When the number of characters in the receiver's FIFO falls below a second predetermined value, an XON character is sent by the receiver to the transmitter. Thereupon, the transmitter resumes transmission. Software flow control can be disabled by the CPU. Since excluding the XON and XOFF characters specifically and completely from the ASCII data stream is undesirable, to avoid an XON or XOFF character sent as data from being recognized as a control character, an "escape sequence" is used in the prior art. That is, when an XON or an XOFF character is to be sent to the transmitter as data, the sequence "ESC XON" or "ESC XOFF" is sent (ESC is the value '1BH A.K.). Under ASCII transfer mode, it is unlikely that the escape sequence ordered "packets". The size of each packet is defined by in the header section at the beginning of each packet. At the end of each packet is a CRC characteristic value, which is recomputed at the receiver. Should a loss of the transmitted data occur, such as resulting from an overflow at the receiver's FIFO, the loss of data would result in a mismatch in the computed CRC characteristic value in the receiver and the corresponding transmitted CRC characteristic value. When such a mismatch occurs, the higher level protocol in the CPU causes the packet in error to be retransmitted. However, under such protocol, not only are packet retransmissions time consuming, such protocols require CPU cycles. Hence, binary data transfer operations in the prior art UARTs are highly inefficient.
In the NS16550 UART, a baud rate generator provides as output a clock signal which is 16 times a user-selected baud rate. To generate the output clock signal, the frequency of a 1.8432 MHz crystal is divided using a 16-bit divisor to achieve baud rates ranging from 50-115.2 KHz. However, as modems of higher speeds are becoming more available, the range of baud rates required by these modems include baud rates higher than 115.2KHz. Thus, to generate a higher baud rate, a higher frequency crystal is required as a time base. However, many existing applications can still be economically provided using the NS1655. Thus, a method to extend the range of supported baud rates without requiring extensive software and hardware modifications in the UART is desired.
In the prior art, UARTs are powered at all times. However, many applications today require low power or battery-powered operation. In those low power operations, it is desirable to provide a method for powering down a UART when data is not actively being transmitted or received. It is also desirable that a powered down a UART can be automatically activated when data arrives at the UART to be either received or transmitted.